Nano-Watt silicon-on-sapphire ADC using 2C-1C capacitor chain

Introduction: Recent years have witnessed remarkable progress in the field of untethered sensors. Many pioneering applications have demonstrated that networks of sensors can greatly advance scientific efforts to understand indoor, natural, civil and tactical environments by providing information from locations that were not reachable before [1]. For wireless sensors, power management is one of the most crucial bottlenecks of the design. Because of the limitation of battery operation in long-term deployments of sensors, self-powered systems have become increasingly attractive [2]. Solar cells and microelectromechanical systems (MEMS) have been widely used in many self-powered systems since their fabrication methods can be combined with IC technology. Because chip-sized energy scavenging devices can provide limited power, sensory circuitry should be designed for ultra-low power budgets [3, 4]. As the interface between the sensing environment and the digital processing module, analogueto-digital converters are crucial to the energy scavenging sensor system’s performance. In this Letter we report an ultra-low power analogue-to-digital converter, which is innovative from three standpoints. First, a 2C-1C capacitor chain implementation is reported, owing to its compact silicon-area and low power consumption. Secondly, a switched capacitor with cascoded inverter is chosen as a high-speed and ultra-low power comparator. Thirdly, because of the combination of the above innovations, this ADC has a power consumption as low as 900 nW at 1.1 V power supply and 1.35 mW at 1.5 V. A recent publication [5] presented a good example of a submW ADC (ADC consumes power less than 1 mW). This Letter focuses on a sub-mW ADC with much larger input range ratio over power supply. When sampling at the same speed of 150 kS=s and a 1 V power supply, this 2C-1C ADC consumes as low as 20% of the power consumed by [5]. A conventional successive approximation architecture is chosen because the simplicity of the design allows for low power consumption, while keeping the sampling rate at high speed. Fig. 1 shows the successive approximation ADC implemented with a 2C-1C capacitor chain. A linearly scaled voltage is delivered by setting and resetting the successive approximation registers. A binary search through all possible quantisation levels is performed before converging to a final digital answer, which is stored in the successive approximation registers.